General False Path Problem in Timing Analysis of Combinational Circuits.

Date of Submission

December 1997

Date of Award

Winter 12-12-1998

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science

Department

Advance Computing and Microelectronics Unit (ACMU-Kolkata)

Supervisor

Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Timing verification can be performed by simulation or by timing analysis. Simu- lation is performed by a simulator which generates the output signals of each com- ponent and compute the delay of cach component according to some delay model and the input signals to the component. Due to the huge computing time required by the simulator, the timing analysis, which takes an input vector-independent approach, is preferred. The timing analysis ignores the operating conditions and functionalities of the components in the design.Based on the connection information and the delay models of components, an acyclic graph is constructed to model the design. The vertices and the edges of the graph represent the components and the connection between the components in the design respectively. The weight associated with a vertex (an edge) is the delay of the corresponding component (the medium delay of the corresponding connection).The delay of a path is represented by the sum of the weights of all vertices and edges involved. Timing analysis is to check the delays of all paths in the graph and to report the paths which violate some timing constraints. Therefore, path selection algorithms which report long paths (referred to as the critical paths and short paths are crucial to the timing analysis approach.But due to the ignoring of operating conditions and functionalities of compo- nents in the design, a path being reported by timing analysis may be a false path. A false path is a path which can never be activated by any input vector. Reporting false paths to the designer provides no useful information for the designer to cor- rect the timing violations. Hence, the timing verifier (the task which implements the timing analysis approach) can detect the long false paths(a false path with a delay greater than a certain threshold T) and report only the long sensitizable paths(a long path which is not a false path) to the designer.In order to avoid reporting the false paths to the designer, some of the previ- ously proposed approaches have tried to use input-vector independent approaches which report the false paths to the basic timing analysis algorithm. However, these algorithms report either a superset or a subset of the actual false path set (We shall discuss this later). Also, these algorithms cannot perform the timing analysis also simultaneously. The major objective of this work is to design and develop efficient and effective algorithms which report all the possible long sensitizable paths and can also be extended to perform the timing analysis simultaneously. A false path is simply a path which is never activated by any input vector. The problem of identifying whether a path (may not be the longest one) is a false path will be referred to as the general false path problem.

Comments

ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843753

Control Number

ISI-DISS-1997-43

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

DOI

http://dspace.isical.ac.in:8080/jspui/handle/10263/6216

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