Design and Implementation of a Redundant Radix-4 Coprocessor with Binary Interface.

Date of Submission

December 1998

Date of Award

Winter 12-12-1999

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sinha, Bhabani Prasad (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Arithmetic Operations in Redundant Radix-4 require lesser time and hardware complexity with respect to those in binary number system. The proposal deals with the Design and Implementation of a coprocessor for some arithmetic and logical operations which can be integrated with the main processor operating in binary mamber system. The implementation is likely to be done using FPGA modules.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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