Design and Implementation of a Redundant Radix-4 Coprocessor with Binary Interface.

Date of Submission

December 1998

Date of Award

Winter 12-12-1999

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science

Department

Advance Computing and Microelectronics Unit (ACMU-Kolkata)

Supervisor

Sinha, Bhabani Prasad (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Arithmetic Operations in Redundant Radix-4 require lesser time and hardware complexity with respect to those in binary number system. The proposal deals with the Design and Implementation of a coprocessor for some arithmetic and logical operations which can be integrated with the main processor operating in binary mamber system. The implementation is likely to be done using FPGA modules.

Comments

ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843109

Control Number

ISI-DISS-1998-63

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

DOI

http://dspace.isical.ac.in:8080/jspui/handle/10263/6226

This document is currently not available here.

Share

COinS