Optimized ATPG for Hardware Trojan Detection.

Date of Submission

December 2016

Date of Award

Winter 12-12-2017

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science

Department

Advance Computing and Microelectronics Unit (ACMU-Kolkata)

Supervisor

Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Combating the threats imposed by hardware Trojans that are covertly inserted in hardware has surfaced as a challenging problem in recent times. An adversary may maliciously tamper the given SoC design at netlist level to insert Trojans for the purpose of extracting secret information from the chip via output pins, or for launching denial-of-service attack. Because of several scalability issues, the detection of hardware Trojans in a large circuit turns out to be extremely difficult when the Trojan sizes are small (∼8−10) gates. Such threats may not only degrade the reliability of the system but also endanger its security, especially when these chips are used for mission-critical applications such as defence, space, biological, and in nuclear stations. As the possible instances of Hardware Trojans present in design are exponential, we propose ATPG-binning technique, using divide-and-conquer strategy, to lessen the search-complexity and then use a SAT-solver to derive a test set. Simulation results demonstrate the effectiveness and superiority of the proposed method to prior work in terms of Trojan-coverage, size of test set, and CPU-time.

Comments

ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843452

Control Number

ISI-DISS-2016-347

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

DOI

http://dspace.isical.ac.in:8080/jspui/handle/10263/6504

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