Power Grid Simulation.

Date of Submission

December 2005

Date of Award

Winter 12-12-2006

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science

Department

Advance Computing and Microelectronics Unit (ACMU-Kolkata)

Supervisor

Sur-Kolay, Susmita (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

VLSI system performance has increased by orders of magnitude in the last few decades. Continued technology scaling and improving transistor performance to increase frequency has made it possible. Increasing integration capacity enabled designers to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue and soon provide integration capacity of billions of transistors. The technology trend of integrating number of transistors was predicted by Moore and is presented below in Figure 1.1. However, this increase in number of devices has made power consumption as barrier. So, this has made the power delivery networks in VLSI circuit design a major design challenge.In micron technology, chips used to have two metal layers for routing signals as well as power and ground. This called for special power and ground routing algorithms and these were usually run before signal routing. But in nanometer technology as the number of devices on chip is increasing, we need to have not only multiple metal layers for proper routing of these nets to devices but also a regular grid like layout for the power delivery network on almost all the metal layers. The power grid is composed of alternate metal lines of power (Vdd) and ground (GND) nets in each layer. The upper and lower metal layers are connected by vertical vias. Typical power grid with three layers is shown in Figure 1.2. Vdd and GND terminals of transistors connect to the lower metal layer vias.The currents and voltages can be analyzed at the vias. Simultaneous switching of transistors connected to the via causes maximum current flow through the via and a droop in voltage. Voltage droop at the via slows the switching of transistors connected to it. If the voltage droop at the via is more than stimulated value, then it makes the circuit faulty and is elaborated below.To lower the total power dissipation, there is also reduction in supply voltage and the corresponding reduction in device threshold voltage. Thus are circuits more Susceptible to noise, including power bus voltage variations. Also, increased density of switching devices and rising frequency has lead to power density problem.The rise in power density with a simultaneous reduction in power supply voltage leads to a large increase in the amount of current thut needs to be delivered.The current demand is incrensing ae epecified ahove but the eupply voltage of modem sub micron VLSI is decreasing day by day. This results in huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, having a serious performance impact. Reduced noise margins may lead to false switching at certain logic gates and latches. Higher logic gate delays, on the other hand, may slow down the eircuit enough so that timing requirements cannot be met. Hence, once voltage drop exceeds certain designer-specified threshold like 30 mv, there is a high probability of faulty behavior of the circuit.Some sources of power fluctuation are IR drop, Ldi/dt-drop, and resonance issues. Traditionally power grid analysis is often emphasized on IR-drop. Recently, due to the rapidly increasing operation frequency, the dynamic power fluctuation caused by Ldl/dt has also become significant. Large numbers of on-chip decoupling capacitors are added to act as temporary on-chip local power supplies for reducing the power fluctuation.

Comments

ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843399

Control Number

ISI-DISS-2005-157

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

DOI

http://dspace.isical.ac.in:8080/jspui/handle/10263/6326

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