Multi-Layer Floorplanning for Partial Reconfiguration of FPGA Devices.
Date of Submission
December 2009
Date of Award
Winter 12-12-2010
Institute Name (Publisher)
Indian Statistical Institute
Document Type
Master's Dissertation
Degree Name
Master of Technology
Subject Name
Computer Science
Department
Advance Computing and Microelectronics Unit (ACMU-Kolkata)
Supervisor
Sur-Kolay, Susmita (ACMU-Kolkata; ISI)
Abstract (Summary of the Work)
Modern Field Programmable Gate Arrays (FPGA) with heterogeneous resources with millions of gates, have been widely used for prototyping large design nowadays. However, large designs might not fit in one FPGA chip. Since, all the modules of a given application might not be active at the same time, the FPGA resources may remain unutilized during the execution of the application. In such applications partial reconfigurability of FPGA helps, where a part of the FPGA chip remains active and inactive part of FPGA could be replaced by another set of modules. Given a schedule of instances with each instance having a set of active modules and their connectivity, a global floorplanning method is essential to reduce the partial reconfiguration overhead while optimizing the performance of the design. This can be done by fixing the position and shapes of common modules across all instances at the same location, while the rest of the temporary modules can be swapped in and out of the board. This is called reconfiguration. Modern FPGAs have different types of resources like CLBs, RAMs and Multipliers. This heterogeneity in resources makes floorplanning in FPGA difficult, especially when the design to be implemented is large. In this dissertation we propose a simulated annealing based multi-layer floorplanning to obtain the fixed positions for the common modules across all instances such that resource requirement of rest of the modules are still satisfied and the total cost of the floorplan is minimized.
Control Number
ISI-DISS-2009-227
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
DOI
http://dspace.isical.ac.in:8080/jspui/handle/10263/6385
Recommended Citation
Chakraborty, Chiranjit, "Multi-Layer Floorplanning for Partial Reconfiguration of FPGA Devices." (2010). Master’s Dissertations. 304.
https://digitalcommons.isical.ac.in/masters-dissertations/304
Comments
ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843338