Scan Path Architecture for Low Power Testing.

Date of Submission

December 2004

Date of Award

Winter 12-12-2005

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science

Department

Advance Computing and Microelectronics Unit (ACMU-Kolkata)

Supervisor

Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

scan design has been applied to the problem of testing sequential circuits as a means of inereasing the controllability and observability of the circuit. Yet the Scan based testing suffer from proionged test application time and excessive test power due to numerous shift operations. During the test mode. filling the test data requires shifting the bits one by one into the scan chain thus creating the increased switching activities in the flip-flops. Average test power can be minimized by minimizing the switching activities in the flip-flops. Modifying the scan chain judiciously may lower both the test application and average test power by minimizing the switching activities. In recent years number of scan architectures are proposed in order to minimize the switching activities and test application time. We have investigated the power consumption. area overheads and hardware overheads of full scanned version of ISCAS89 benchmark circuits for different architecture namely Single Serial Scan Architecture and Double Tree Scan architecture.

Comments

ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843263

Control Number

ISI-DISS-2004-122

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

DOI

http://dspace.isical.ac.in:8080/jspui/handle/10263/6292

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