Floorplan Equipartitioning using Staircase Channel Minimizing the Crossing Nets.

Date of Submission

December 1997

Date of Award

Winter 12-12-1998

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Nandy, Subhas Chandra (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

This dissertation identifies a new problem of partitioning of VLSI floorplan called Balanced monotone staircase partitioning. In a VLSI floorplan, the isothetic rectangular circuit modules are placed on a 2D floorplan and the net attached to each module is given. The objective of global routing is to connect the terminals attached to different modules that belongs to the same net. In this framework the global routing problem is mapped into a series of hierarchical staircase channel routing. So our objective is to divide the floor into two almost equal halves by a monotone staircase channel and simultenously minimize the number of crossing nets. We have defiued a mixed optimization problem where the objective function is a convex combination of the following two ratios:A ratio = difference in area of two partitions/ Total-area.Nratio= number of crossing net/Total-net.The problem of partitioning the floor into almost two equal halves is shown to be NP-COMPLETE in (2). Here we present a heuristic algorithm using circuit partitioning algorithm given by Fiduccia-Mattheyses[6]. Finally we have suggested a new approach to soive the problem.


ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843185

Control Number


Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.



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