Implementations of FAST and AEZ on field programmable gate arrays for low level encryption of disks with 4096-byte sectors

Authors

• Debrup Chakraborty, Indian Statistical Institute, Kolkata
• Sebati Ghosh, University of York
• Cuauhtemoc Mancillas López, Centro de Investigacion y de Estudios Avanzados del Instituto Politécnico Nacional
• Palash Sarkar, Indian Statistical Institute, Kolkata

Article Type

Research Article

Publication Title

Journal of Cryptographic Engineering

Abstract

A fixed length tweakable enciphering scheme (TES) is the appropriate cryptographic functionality for low level disk encryption. Research on TES over the last two decades have led to a number of proposals, some of which have been implemented using field programmable gate arrays (FPGAs). This paper considers FPGA implementations targeted at disks supporting 4096-byte sectors. We choose two schemes, namely AEZ and FAST, for implementation and provide detailed rationale for our choice. The relevant architectures are described and simulation results on the Xilinx Virtex 5 and Virtex 7 FPGAs are presented. For comparison, we consider previous implementation of the IEEE standard EME2. The results indicate that FAST outperforms the other schemes.

DOI

10.1007/s13389-025-00384-6

Publication Date

11-1-2025

Recommended Citation

Chakraborty, Debrup; Ghosh, Sebati; López, Cuauhtemoc Mancillas; and Sarkar, Palash, "Implementations of FAST and AEZ on field programmable gate arrays for low level encryption of disks with 4096-byte sectors" (2025). Journal Articles. 5422.
https://digitalcommons.isical.ac.in/journal-articles/5422