Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis

Article Type

Research Article

Publication Title

Microprocessors and Microsystems

Abstract

The design process of the JPEG-CODEC as a reusable hardware intellectual property (IP) core for electronic and multimedia systems involves conflicting design goals such as area and latency, alongside providing hardware security against IP piracy and false claims of IP ownership during high-level synthesis (HLS). The proposed work introduces the following novelties: (a) firefly algorithm (FFA)-driven design space exploration (DSE) for generating optimal design solution of secure JPEG-CODEC hardware IP design during HLS, (b) covert security constraints generation process based on key-driven crypto-chain driven hardware security methodology during performing area-latency tradeoff, (c) embedding process that integrates covert security constraints into the design of the JPEG-CODEC. The proposed approach enables the detection of IP piracy and false IP ownership claim. The proposed methodology obtains stronger tamper tolerance ability of > ∼10,116 times and enhanced digital evidence (probability of coincidence) of > ∼102 times than similar recent techniques at lesser design cost. Moreover, the proposed approach attains stronger entropy value of > ∼1078 times than similar recent techniques.

DOI

https://10.1016/j.micpro.2023.104916

Publication Date

10-1-2023

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