Date of Submission
4-28-2020
Date of Award
4-28-2021
Institute Name (Publisher)
Indian Statistical Institute
Document Type
Doctoral Thesis
Degree Name
Doctor of Philosophy
Subject Name
Computer Science
Department
Advance Computing and Microelectronics Unit (ACMU-Kolkata)
Supervisor
Bhattacharaya, Bhargab Bikram (ACMU-Kolkata; ISI)
Abstract (Summary of the Work)
Today’s integrated circuits comprise billions of interconnected transistors assembled on a tiny silicon chip, and testing them to ensure functional and timing correctness continues to be a major challenge to designers and test engineers with further downscaling of transistors. Although substantial progress has been witnessed during the last five decades in the area of algorithmic test generation and fault diagnosis, applications of combinatorial and machinelearning (ML) techniques to solve these problems remain largely unexplored till date. In this thesis, we study three problems in the context of digital logic test and diagnosis. The first problem is that of fault diagnosis and can be stated as follows. Given the output syndromes for test responses in a circuit-under-test (CUT), localize the fault (root-cause) in the netlist; solution to this problem is required in order to fine-tune the process technology and to improve yield in subsequent production cycles. The second problem deals with the issue of unknown logic value (X) and answers the following question. Given a CUT and a test set T, how the fault-coverage of T is impacted when an unknown logic value (X) arrives at one of its inputs. Is there any computationally efficient mechanism to grade the CUT-inputs based on their X-sensitivity? A solution to this problem is needed in X-cancellation for optimizing test costs and to improve reliability. In the third problem, we investigate, given a CUT, how the structure of the underlying network can be represented in a compact and lossless form, so as to make them easily readable by ML-tools for test and diagnostic purposes. This is a classical problem of representing directed graphs that facilitates feature extraction. We present a combinatorial solution to the first problem, a learning-based technique to handle the second problem, and a novel solution to the third problem that relies on Pr¨ufer sequence.
Control Number
ISILib-TH472
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
DOI
http://dspace.isical.ac.in:8080/jspui/handle/10263/2146
Recommended Citation
Pradhan, Manjari Dr., "Studies on Diagnostic Coverage and X-Sensitivity in Logic Circuits." (2021). Doctoral Theses. 440.
https://digitalcommons.isical.ac.in/doctoral-theses/440
Comments
ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843860