A Novel EPE Aware Hybrid Global Route Planner after Floorplanning
Document Type
Conference Article
Publication Title
Proceedings of the IEEE International Conference on VLSI Design
Abstract
IC fabrication in nanometer technology nodes faces severe challenges in handling lithography hotspots due to edge placement error (EPE). These hotspots are particularly tackled by wire-spreading or rip-up and reroute during detailed routing, at the cost of more design iterations. They cannot be minimized unless a suitable routing penalty is imposed during global routing. In this paper, we present a new hybrid global route planning framework that follows floor planning. Since an accurate estimation of EPE on a net segment cannot be attained, we employ a routing penalty based on known simulation results, in order to identify a least cost routing path of a net across multiple metal layers. The results of our experiments on IBM HB floor planning benchmarks show an 4%, 53% and 74% improvement in net length, via count and worst case congestion respectively on an average.
First Page
595
Last Page
596
DOI
10.1109/VLSID.2016.102
Publication Date
3-16-2016
Recommended Citation
Kar, Bapi; Sur-Kolay, Susmita; and Mandal, Chittaranjan, "A Novel EPE Aware Hybrid Global Route Planner after Floorplanning" (2016). Conference Articles. 655.
https://digitalcommons.isical.ac.in/conf-articles/655
