Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template

Document Type

Conference Article

Publication Title

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

Abstract

This paper presents a novel methodology to design fault secured JPEG-compression-decompression (codec) hardware accelerator with piracy detective control using secure fingerprint template of intellectual property (IP) vendor. In the proposed approach, firstly, the fault secured schedule for JPEG-codec design is generated from its behavioral description. Subsequently, in order to enable detective control against piracy, secure digital template corresponding to fingerprint biometric of IP vendor is generated and implanted into the design. In order to do so, firstly, fingerprint features are transformed based on IP vendor specified key-set. Subsequently, the generated secure fingerprint template in the form of encoded hardware security constraints is implanted into the design during behavioral/ high-level synthesis phase of integrated circuit (IC) design. The implanted hardware security constraints thereby ensure the seamless detection and isolation of fake/pirated design versions during piracy detection process, before their conjunction into system on chip (SoC) of electronic systems. The proposed approach achieves the following: i) fault secured hardware accelerator for JPEG-codec with integrated piracy detective control at negligible design cost overhead ii) higher resiliency against tampering attack and iii) lower probability of coincidence (indicating definitive proof of ownership for genuine IP vendor).

DOI

10.1109/DFT59622.2023.10313536

Publication Date

1-1-2023

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