FPGA-based IP and SoC security

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Book Chapter

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Fundamentals of IP and SoC Security: Design, Verification, and Debug


Intellectual property (IP) cores in FPGAs are being used widely as these provide high flexibility and efficiency at low cost and low time-to-market. An IP in FPGA is primarily a HDL design or a bitfile for the same. Security aspects have specific issues for the FPGA IP cores. Partial recon gurability of an FPGA has introduced further security holes. A bitfile or a partial bitstream is loaded on an FPGA architecture in encrypted form in order to prevent unauthorized access of the IP. This encryption of the bitfile may be cracked through side-channel attacks. For authentication of a genuine IP vendor and an authorized IP user, their binary signatures may be included in the FPGA bitstream. However, maintaining resilience of the signatures against tampering is a challenge in case of their public verification. Another recent challenge in FPGAs due to hardware Trojans or extraneous circuitry inserted surreptitiously is being combated with parity-based detection techniques. However, it is still hard for the standard FPGA tools to detect Trojan circuits inserted directly in the bitfile cores. In case of a system-on-a-chip (SoC) implemented with FPGAs, the security issues in IP distribution, IP management, and inter-communication are even more complex and challenging. This chapter elaborates the various security techniques adopted in FPGAs, security measures remain as research proposal, along with several alarming security threats open for research.

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