Tree-Based Hybrid Scan Architecture for VLSI Testing.
Date of Submission
December 2007
Date of Award
Winter 12-12-2008
Institute Name (Publisher)
Indian Statistical Institute
Document Type
Master's Dissertation
Degree Name
Master of Technology
Subject Name
Computer Science
Department
Advance Computing and Microelectronics Unit (ACMU-Kolkata)
Supervisor
Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)
Abstract (Summary of the Work)
Full scan based design technique is widely used to alleviate the complexity of test generation for sequential circuits. However, this approach leads to substantial increase in the test application time, because of serial loading of test vectors, especially in today’s digital circuit containing thousands of flip-flops. In a scan-based system with a large number of flip-flops, a major component of power is consumed during scan-shift and clock operation in test mode. In this thesis, a novel two-stage hybrid DFT approach is proposed that drastically reduces the scan-shift and clock activity during testing. The design is independent of the structure of the circuit-under-test (CUT) or its test set. A tree-type structure is employed to design the scan architecture incorporating very simplified hardware circuitry. It provides a significant reduction both in instaneous and average power needed for clocking and scan shifting. It reduces the number of test vectors compared to autoscan technique. The test suite consists of: (i) some externally deterministic test vectors to be scanned in where flip-flops are oriented in tree-type structure, (ii) internally generated responses of the CUT to be re-applied as tests iteratively, in non-scan mode, (iii) a set of externally deterministic test vectors to be scanned in where flip-flop are interconnected in linear scan chain. The method uses only combinational ATPG for deterministic testing and thus makes a good use of scan based and non-scan testing. Experimental results on ISCAS-89 benchmark circuits reveal a significant reduction of test application time and energy/power reduction due to shift in test mode.The architecture fits well to built-in self-test (BIST) scheme.
Control Number
ISI-DISS-2007-211
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
DOI
http://dspace.isical.ac.in:8080/jspui/handle/10263/6374
Recommended Citation
Lahiri, Subhra, "Tree-Based Hybrid Scan Architecture for VLSI Testing." (2008). Master’s Dissertations. 379.
https://digitalcommons.isical.ac.in/masters-dissertations/379
Comments
ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843712