Studies on Isomorphic-Redundancy and Testing of Non-Scan Sequential Circuits.

Date of Submission

December 1992

Date of Award

Winter 12-12-1993

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Synthesizing a sequential circuit from the description of state transition graph (STG) involves the steps of state minimization, state assignment and logic optimization. One of the basic goals in synthesis of non-scan sequential circuit is to make the circuit fully testable. Test sequences for all single stuck-at faults in the synthesized machine be derived using test can generation algorithms on the combinational logic blocks of the machine. A circuit is said to be 100% testable if test vectors can be generated for all the lines in the circuit under the single stuck-at fault model. The presence of redundant faults prevent the circuit from being fully testable. There two classes of are redundant faults in sequential circuit, namely, a non-scan combinationally and sequentially redundant faults.This part of the dissertation deals with the study of one special class of sequential redundant faults (SRFS), called isomorphic faults (Isomor ph-SRF ). Such a fault causes the STG of the faulty machine to be isomorphic to that of the fault-free machine. No input-out put experiment can thus detect i somorphic an fault. An open question in this context is whether there exists a combinationally real sequential circuit that is reduced and irredundant, in which a single-stuck at fault creates an isomorphic faulty machine. This dissertation settles this open question which shows that such a machine indeed exists.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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