Algorithm for Mapping Boolean Network to LUT Based FPGAs.

Date of Submission

December 2001

Date of Award

Winter 12-12-2002

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sur-Kolay, Susmita (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Field Programmable Gate Arrays (FPGAS) have become one of the most popular implementation media for digital circuits. The key to FPGAS popularity is the ability to implement any circuit simply by appropriately programming an FPGA. Other circuit implementation options, such as Standard Cells or Mask Programmed Gate Arrays (MPGAS), require that a different VLSI chip be newly fabricated for each design. The use of a standard FPGAS has two key benefits: lower non-recurring engineering (NRE) cost and faster time to market.All FPGAS are composed of three fundamental components: logic blocks, 1/0 blocks and programmable routing. A circuit is implemented in an FPGA by programming each of the logic blocks to implement a small portion of the logic required by the circuit, and each of the 1/O blocks to act as either an input pad or an output pad, as required by the circuit. The programmable routing is configured to make all necessary connections between logic blocks and from logic blocks to 1/O blocks.1.2 FPGA programming technologiesThere are three different approaches of making FPGAS programmable. The most popular technology today uses SRAM cells to control pass transistors, multiplexers, and tri-state buffers in order to configure the programmable routing and logic blocks as required. Pass gates are implemented with nMOS pass transistors because this results in higher speed due to higher carrier mobility in NMOS technologies are antifuses and floating gate devices.The logic blocks used in an FPGA strongly influences the FPGA speed and area efficiency. While many different logic blocks have been used in FPGAS, most current commercial FPGAS use logic blocks based on look-up-tables (LUTS). Figure 1.2 shows how a 2-input LUT can be implemented in an SRAM based FPGA -- a K-input LUT requires 2k SRAM cells and a 2k -input multiplexer. A K-input LUT can implement any function of K-inputs; one simply programs the 2 desired function. SRAM cells to be the truth table of the desired function.1.3 Designing with FPGASThe problem of determining how to map a circuit into an FPGA is normally broken down into the steps given in Figure 1.3 The step for synthesis to logic block first converts the circuit description into a net list of basic gates. Then this list of basic gates is converted to a net list of FPGA logic blocks such that the number of logic blocks needed is minimum and/or circuit speed is maximum. The conversion from a net list of basic gates to a net list of logic blocks can be divided into the steps given in Figure 1.4Logic optimization stop removes redundant logic and simplifies logic whenever possible. This step does not consider the type of elements by which the final circuit is implemented, so it is called technology independent logic optimization.In the technology mapping step respecting the limitations of the target FPGA, the optimized net list of basic gates is mapped to LUTS. In this step optimization is done to reduce the number of LUTS and/or the number of levels.1.4 ScopeIn this report we are dealing with some aspects of technology mapping problem.


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Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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