Redundant Radix-4 Coprocessor Architecture Implementation.

Date of Submission

December 1999

Date of Award

Winter 12-12-2000

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sinha, Bhabani Prasad (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Development of coprocessors for performing specific set of the host processor's operations has been a good choice for improving the host processor's performance. Arithmetic operations like addition and multiplication of redundant radix - 4 numbers can be done in O(1) time and O(log n) time respectively [1].This gives the motivation to develop a high speed redundant radix - 4 coprocessor (RR - 4 coprocessor) which can perform all arithmetic operations of the host processor. A detailed account of RR - 4 arithmetic, binary to RR -4 conversion and the re-conversion is given in (1] and will not be repeated. Logic for addition, multiplication also has bcen developed [1]. We consider a closcly coupled configuration of the host processor and the coprocessor wherein both the host processor and the coprocessor share the same bus control logic and clock. This report deals with the various aspects of design of coprocessor and the implementation details. Some code segments are also included for reference purpose. Implementation has been done in Verilog Hardware Description Language[2]. The model coprocessor does only integer operations and hence division operation has not been implemented due to floating point considerations. Veriwell Corp.'s Evaluation compiler for verilog was used for simulation purpose.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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