Tracing the Hot Spots for Placement of Heat Sink in a VLSI Chip Layout.

Date of Submission

December 2004

Date of Award

Winter 12-12-2005

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

In today's VLSI technology the chip area is shrinking fast in order to meet speed and performance criteria. With the reduction in chip area critical factors like power consumption, power density, and propagation delay come into play. The heat generated due to the power consumption by various elements is radiated through the substrate. Due to reduction in chip size area this accumulated heat may attain very high levels, and consequently the power density may exceed a threshold value at some points on the layout causing thermal damage to the chip. In this dissertation, a geometric approach is presented to model and identify these hot spots. Results based on simulation are also reported.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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