General Recursive Staircase Bipartition Scheme for VLSI Floor Plan Layout with Simultaneous Minimization of Net Crossovers.

Date of Submission

December 2007

Date of Award

Winter 12-12-2008

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Motivation: In DSM (deep submicron) VLSI, interconnect delay plays a major role in determining system performance, reliability and cost. To ensure timing closure of designs, impacts of interconnect should be incorporated as early as possible in the design flow. There are several approaches to mitigate the interconnect delays. Repeater insertion is widely accepted approach to minimize delay.Our work is primarily a recursive bi-partitioning of a floorplan layout with staircase channels which is aware of repeater overlap and congestion. This scheme doesn’t directly deals with repeater placement but it reveal a global interconnect planning which will facilitate repeater placement in routing stage. The basic bi-partition algorithm is primarily based on stair-case bipartition scheme proposed by Dasgupta et.all. Some modification is incorporated to meet our requirement. This is a top-down approach. The algorithm recursively divides the floorplan into two equal halves with a monotone staircase path or staircase channel. At each level of the hierarchical channel, using a simple channel scan based heuristic, cross over is minimized. Reason is to reduce the overlap of repeater form different nets that are to be inserted in the channel. It is observed that pins on both side of channel which is in the deepest level of partitioning (it is those channel which separates only two adjacent blocks) are to be connected individually. And going higher up the channel order it is sufficient to connect any two pins of same net form either side of the channel. This considerably reduces routing overhead. It is also worth mentioning, this is a general bipartition scheme as it works equally well for both slicing and non-slicing floorplan.Problem formulation:Definition: A monotone staircase path P= {l1, l2, l3, l4 ….ln} is a set of line segments such that ( i) two line segment li, li+1 share a common end and they are either horizontal or vertical to each other. (ii) let ai=(xi,yi) and ai+1=(xi+1,yi+1) be two point belonging to line segment li, li+1 respectively , then i either (1). xi ≤ xi+1 and yi ≤ yi+1or (2) xi ≤ xi+1 and yi ≥ yi+1Problem formulation : Given a rectangular floorplan F={R1,R2,R3…..Rm} find a set of hierarchical monotone staircase path PF= {(p1),(p11,p12),(p111,p112,p121,p122)….}such that i) p1 divides F into two half say FP11 and FP12 with either equal number of blocks or one extra in any one of the half (equal if even number of blocks in the floorplan) and the next level of path p11,p12 divides FP11 and FP12 further maintaining the equality condition. This partitioning continues until the given floorplan is disintegrated to individual rectangles.ii) The cross-over of nets in each hierarchical path is minimized.Overview of the work:In total there are four steps: i) parsing of the input file. ii) Floorplan graph generation from the parsed data. iii) Generation of slicing tree with staircase channels– this main part of the procedure. iv)Minimization of crossing of nets in each channel. Three procedures (ii, iii & iv) are used simultaneously and recursively to divide the floorplan individual rectangular blocks and a complete staircases slicing tree is generated. The leaf nodes of this tree are the rectangle blocks of the floorplan.


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Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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