Function Extraction & Verification of General MOS Transistor Circuits.

Date of Submission

December 1997

Date of Award

Winter 12-12-1998

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

There is a natural tendency to make the VLSI design as a interconnected set of clusters of transistors, which can be utilized to extract the function from an MOS transistor network. The other requirement of verification of the circuit can also be performed simultaneously. In this dissertation, we present an algorithm for partitioning a switch level ( nMOS / PMOS / CMOS ) network, which may be a multicell, into several blocks and then extract the logical function from each of the individual components, followed by evaluation of the overall logic. Extension of this technique to sequential circuits is also straightforward.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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