SAT Solver Based Multi Cycle Droop Fault Testing.

Date of Submission

December 2009

Date of Award

Winter 12-12-2010

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sur-Kolay, Susmita (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Driven by Moore’s Law for more than four decades, the complexity and scale of VLSI integration has reached unforeseeable heights today. The increased density of switching devices and rising frequency has led to large power consumptions per unit area. Due to high frequency of operation and inductive effects of the power grid lines, a noticeable power drop occurs when logic gates within close physical proximity of each other switch simultaneously. This drop in power, known as droop, propagates along the power supply lines, decaying exponentially with spatial and temporal distance from its origin. This is manifest a few clock cycles later, in the form of a reduced power drop at a neighboring via, giving rise to the possibility of timing faults at some gates in that via. Such faults are known as multi cycle droop faults (MDF). In this dissertation, a new approach is taken towards modeling of these faults in combinational circuits, using the concepts of Boolean Satisfiability to provide more flexibility and efficiency in test generation for detection of these faults. Finally, a prototype algorithm to generate test vectors for multi-cycle droop faults in full-scan circuits is presented and discussed.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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