Effect of Circuit Structure on Path Delay Fault Testability in Vlsi Design.

Date of Submission

December 1998

Date of Award

Winter 12-12-1999

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Bhattacharya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Failure that cause logic circuits to malfunction at the desired clock rate and thus violate timing specifications are currently receiving much attention .Such failures are modeled as delay faults. They facilitate delay testing. Since design for testability is the approach followed now-a-days several synthesis for path delay fault (PDF) testability is studied in much depth. Local transformation is one such approach. A new approach for applying local transformations is considered here. This approach can be used along with the existing local transformation approaches to get better results.Additionally , a software implementation of the proposed algorithm is also considered here and the experimental results are quiet attractive in comparison to existing local transformation algorithms.


ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843216

Control Number


Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.



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