Memory Aware Scheduling in Mixed Criticality Systems.

Date of Submission

December 2017

Date of Award

Winter 12-12-2018

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Banerjee, Ansuman (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Mixed criticality systems integrate tasks of different criticality levels on the same platform. In order to ensure safety of such systems, we need to guarantee that all critical tasks must complete their execution prior to their deadlines. In normal architectural platforms, DRAM controllers generally serve the memory requests on an open page policy. So DRAM controllers that are used in normal architecture cannot serve all the memory requests and hence all the tasks often cannot meet their deadlines. In this work, we propose a novel approach for bank aware memory allocation of tasks which can significantly improve the performance of these mixed criticality systems. Experimental results on different benchmarks show the efficacy of our proposed scheme.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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