Partial Reconfiguration of Field Programmable Gate Array Devices using Xilinx Architecture.

Date of Submission

December 2007

Date of Award

Winter 12-12-2008

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sur-Kolay, Susmita (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Field Programmable Gate Arrays (FPGA) are specific integrated circuits that can be programmed by users easily. The FPGA contains versatile functions, configurable interconnects and input/output interface to adapt to the user specification. It has a bunch of simple, configurable logic blocks arranged in an array with interspersed switches that can rearrange the interconnections between the logic blocks. Each logic block is individually programmed to perform a logic function (such as AND, OR, XOR, etc.) and then the switches are programmed to connect the blocks so that the complete logic functions are implemented. FPGA allow rapid prototyping using custom logic structures, and are very popular for limited production products. Modern FPGA are extremely dense, with complexity of several millions of gates which enable the emulation of complex hardwares such as parallel microprocessors, mixture of processor and signal processing chips etc.One key advantage of FPGA is their ability to be reprogrammed, in order to create a completely different hardware by modifying the logic gate array. Now-a-days FPGA not only exists as simple component, but also as macro-blocks in systemon-chip designs. In the case of communication systems, the configurable logic may be dynamically changed to adapt to improved communication protocol. In the case of very low power systems, the configurable logic may handle several different tasks in series, rather than embedding all corresponding hardware that never works in parallel.1.2 MotivationAs we have mentioned that in several cases we have a series of different tasks those never runs in parallel. In these cases what is usually done is reconfiguring the system totally whenever one task is finished and the next task is triggered.Configuration of logic for an FPGA is done by using dedicated CAD tools. The subsequent steps in the flow consist of partitioning the circuit, floor-planning on the board followed by placement and routing. The entire flow is handled by CAD tools meant for FPGAs. Now the main advantage of using FPGA in these kinds of applications is that we are utilizing the non parallel nature of the tasks in the process of reconfiguring the same hardware. This saves a huge cost in terms of hardware resource requirements. But one of the problems of this method is the reconfiguration time needed for transition between two tasks. Because for the subsequent task we have to load the new design to CAD tool, configure logic blocks by dumping the design to board followed by the floorplan, place and route stages.To come up with a possible solution to this problem instead of going for a total reconfiguration of the FPGA device, the concept of partial reconfiguration is creeping in. This is possible because most of the applications are such that we will have some part of the designs similar between different tasks. So in consecutive stages we don’t need to configure the entire device if by some means we can keep the common part from the earlier instance unaffected. We have to configure rest portion of the device, not the entire one. This is the essence of Partial Reconfiguration.1.3 Scopes & BenefitsPartial Reconfiguration in FPGA devices has a very wide scope of practical purpose applications where some online application or communication is active. Partial reconfiguration offers countless benefits across multiple industries. It can be an important component to any design or application– allowing designers more capabilities and resources than meets the eye.Partial reconfiguration is the ability to reconfigure selected areas of an FPGA anytime after its initial configuration. We can do this while the design is operational and the device is active (known as active partial reconfiguration) or when the device is inactive in shutdown mode (known as static partial reconfiguration).


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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