Multi Cycle Droop Fault in Combinational Circuits.

Date of Submission

December 2008

Date of Award

Winter 12-12-2009

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Master's Dissertation

Degree Name

Master of Technology

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sur-Kolay, Susmita (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

The scale of integration in VLSI chips is soaring, thereby the power consumption per unit area and also per unit length of power supply lines is increasing phenomenally. As the logic gates in physical proximity switch simultaneously, a noticeable power drop, known as droop, occurs at the power via nearest to these gates due to high frequency of operation and inductive effects of the narrow grid lines. Further, this drop propagates along the power supply lines, exponentially decaying in both time and the distance from the origin of droop, and thus causing a power drop even a few cycles later at some distant via. This may result in timing faults at few logic gates at that via. These faults are termed as multi cycle droop faults (MDF). Modeling of these faults and understanding their behavior is yet to be explored. In this dissertation, a new model of multi cycle droop faults is first proposed at gate level granularity. But for the sake of efficiency of test generation, this is approximated by a model at via level granularity. Finally, a simple ATPG based procedure to generate test patterns for these faults is presented along with preliminary results for few ISCAS85 benchmark circuits.


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Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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