Shared Pattern History Tables in Multicomponent Branch Predictors with a Dealiasing Cache
IEEE Embedded Systems Letters
In this letter, we study the problem of designing multicomponent branch predictors for low-resource embedded systems. The highlight of our design is a shared pattern history table with a tiny dealiasing cache for intercomponent interference resolution. Experiments on the CBP-5 traces are shown to record the performance in terms of prediction accuracy. Synthesis results generated using the Synopsys design compiler with TSMC 90-nm libraries confirm the area and power benefits of our design.
Das, Moumita; Banerjee, Ansuman; Chaudhuri, Mainak; and Sardar, Bhaskar, "Shared Pattern History Tables in Multicomponent Branch Predictors with a Dealiasing Cache" (2020). Journal Articles. 164.