Date of Submission


Date of Award


Institute Name (Publisher)

Indian Statistical Institute

Document Type

Doctoral Thesis

Degree Name

Doctor of Philosophy

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Sinha, Bhabani Prasad (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

Many real-life applications in the areas of signal processing, image processing, etc., require a large amount of fast computations to be performed. Although high speed powerful processors are currently available due to the phenomenal advances in VLSI technology, the increasing demand for massive real-time computations can not be met just by a uniprocessor system. One way of achieving the goal of fast computation is through parallel processing. In parallel processing, a problem is broken into several subproblems, which are distributed among different processors so that each of the processors can perform its task simultaneously. Main areas of recent research in parallel processing include parallel architectures and algorithms, parallel models and complexity classes, programming languages, operating systems and compilers for parallel computers, ete.Interprocessor communication in a parallel processing system is effected through either a shared memory or an interconnection network. Interconnection networks may be of two types : (1) static and (ii) dynamic. In static interconnection net- works, there are fixed links among the nodes for which the connection pattern can not be changed. On the other hand, in dynamic interconnection networks, the interconnections among the nodes are made through links and switches and as a result, different input-output connections can be established by changing the switch settings. A static interconnection network is usually represented by means of a network graph. The nodes of this graph represent. the processors and the edges stand for the interprocessor links. A good network topology should have the following desírable features : i) small number of links to reduce the cost of interconnection, ii) low node degree to limit the number of I/O ports per processor, iii) low diameter to reduce the inter processor communication delay, iv) high degree of fault tolerance, v) regularity, vi) symmetry, vii) incremental extensibility, viiüi) high bisection width, ix) easy routing scheme in fault free as well as faulty situations, x) ease of mapping algorithms, etc.The problem of designing a network topology, simultaneously satisfying all the above requirements, is very difficult as some of them are mutually conficting. For example, the objectives of achieving low diameter as well as low node degree are in conflict with each other. Diameter can be reduced by introducing more links in the topology which, in turn, increases the node degrec. Fault tolerance of the network is another issue which is also increased with increase in node degree. The usual approach to deal with all these problems is to design a near-optimal topology that offers a fair compromise among the above requirements, depending on the needs approach to deal with all these problems is to design a near-optimal topology that offers a fair compromise among the above requirements, depending on the needs of the specific application. Designing such a network topology constitutes one of the interesting areas of research in parallel processing.Ring, mesh, tree, hypercube, [A89), (L92), etc., are some examples of popular static networks. Ring topology is widely used mainly due to its structural symmetry and simplicity. Although the routing algorithm in this network is very simple, it suffers from a large communication delay. This communication delay can be reduced if additional links are introduced within a ring in a uniform way. One possible topology resulting from such modifications is the distributed loop network [BT91]. Variations of such modifications leave ample scope for further research.


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Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


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