Date of Submission


Date of Award


Institute Name (Publisher)

Indian Statistical Institute

Document Type

Doctoral Thesis

Degree Name

Doctor of Philosophy

Subject Name

Computer Science


Advance Computing and Microelectronics Unit (ACMU-Kolkata)


Bhattacharaya, Bhargab Bikram (ACMU-Kolkata; ISI)

Abstract (Summary of the Work)

The term Very Large Scale Integration (VLSI) reflects the capability of semi- conductor industry to fabricate a complex electronic circuit consisting of millions of components on a single silicon substrate. The growth of semiconductor technol- ogy in recent years has been described by "Moore's law", enunciated in the late 1960s, which projected quadrupling of components in a chip in every three to four years. Several factors contributed to this tremendous growth : (i) reduction of line width of the basic device and interconnection wires due to the development of high- resolution lithographic techniques and improved processing capabilities, (ii) increase in the size of the silicon wafer due to improved reliability of processing, (ii) growth of the accumulated circuit, and (iv) layout design experience. Better understanding of system level design issues leads to improved architectures exploiting the current technology, and helps in designing efficient electronic design automation (EDA) tools for logic synthesis, circuit layout, simulation, verification, and testing.Microelectronics technology is advancing very rapidly. The design styles and tools are also undergoing a continuous evolution. The custom design style incorporates maximum flexibility; the designers have at their disposal the entire array of design tools, i.e., logic capture, layout, design verification, simulation, timing verification, placement and routing.VLSI technology plays a major role in the development of complex electronic systems. As a result of continuing progress in semiconductor technology, around 100,000 to several millions of transistors can now be put on a single micro-chip. New design methods for VLSI are therefore of constant need to cope with this increased design complexity.The VLSI design process spans a diverse spectrum of disciplines in physics, chemi- cal engineering, electrical engineering, and computer science, Because of the diver- sity of tasks and design issues, a systematic approach to breaking the process into a number of design layers and subtasks is essential. Typically, the top-down design of a chip consists of the following stages:(i)O design specification (ii) functional design(iii) logic design (iv) circuit design(v) physical design(vi) fabrication on semiconductor chips.Each stage consists of synthesis, analysis and verification, and iterations may be necessary in order to eliminate errors. Layout design is essentially a stage of physical design where behavioral and structural representations of an electronic system are translated to geometric shapes to be used during fabrication. Several problems arise during the layout design of VLSI chips. This includes partitioning the components into homogeneous groups, placement of modules on the floor and finally, routing, i.e., interconnection (wiring) among the modules.The work reported in this thesis is mainly concerned with the development of new and efficient routing algorithms. Once a circuit is partitioned and elements are placed on board, it is necessary to implement the connection patterns amongst the modules using signal nets.The objective of routing strongly depends on the nature of the chip. For general purpose chips, it may be sufficient to minimize the total wire length in order to reduce the chip area. For high performance chips, total wire length may not be a major concern. Instead, one may want to minimize the length of the longest wire to minimize the delay in signal propagation and, to reduce crosstalk to enhance its performance. The presence of large number of vias (contact holes across layers) is undesirable from fabrication and circuit performance point of view. So, via minimization also plays an important role in designing routing algorithms, Similar other parameters need to be considered depending on the design goals.


ProQuest Collection ID:

Control Number


Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


Included in

Mathematics Commons