Test-Time Reduction for Power-Aware 3D-SoC
Proceedings of the IEEE International Conference on VLSI Design
Minimization of overall test time is one of the primary concerns in the design of 3D-SoCs, whereas satisfying the thermal constraints and bounding the number of inter-layer TSVs are also of critical importance. This paper presents a scheduling-based technique to reduce test-Time for core-based 3DSoCs, under certain constraints on TAM-width and the number of TSVs. A partitioning technique is also suggested to assign the layers to cores under TSV and power constraints. The proposed methods have been tested on several SoC benchmarks. Experimental results reveal an improvement in test time for most of the circuits, while satisfying the above-mentioned constraints.
Banerjee, Sabyasachee; Majumder, Subhashis; and Bhattacharya, Bhargab B., "Test-Time Reduction for Power-Aware 3D-SoC" (2018). Conference Articles. 96.