Reliability-aware test methodology for detecting short-channel faults in on-chip networks

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Conference Article

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems


With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, short-channel faults in an NoC often cause system-level failures that may have significant impact on its performance. This paper proposes a cluster-based distributed scheme for online testing of short faults in NoC channels. The proposed algorithm detects both intra and interchannel short faults and identifies the underlying faulty channel-wires connected to a node. The nodes in a cluster-set are appropriately scheduled to reduce test time. The approach scales to larger NoCs irrespective of size of the network and channel width. The proposed scheme also extends its application from regular to irregular NoCs, and to other channel faults like open. Fault simulation shows that the proposed cluster-driven scheme is capable of detecting all modeled short-channel faults. Online evaluation of the scheme also reveals the extent of impact that the short faults impart on various performance metrics for large traffic. Compared to prior work, it reduces hardware area overhead up to 27% and test time by more than 21 × on several test cases. In addition, packet latency and energy consumption are reduced by 19.47%-40.16% and 17.57%-34.20%, respectively.

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