Fault Testing in AI-Accelerators: A Review

Document Type

Conference Article

Publication Title

Proceedings of the Asian Test Symposium

Abstract

With the emergence of all-inclusive AI/ML applications, hardware solutions, commonly known as AI-Accelerators (AIA), are now being widely adopted to emulate deep neural networks (DNN) to facilitate faster and large-scale data analytics. An AIA-chip comprises a 2D systolic array of identical processing units (PEs), registers, and glue logic. These arrays may be implemented with traditional digital logic or with analog primitives such as memristors. As the packing density of AIA-chips increases, they become vulnerable to various manufacturing defects thereby compromising yield and the accuracy of prediction. In this review article, we summarize various methods that have been recently proposed for expediting Automatic Test-Pattern Generation (ATPG) for stuck-at and transition faults in AIA-arrays. Other relevant issues such as fault-criticality, self-test, fault-recovery, and the asymmetry of fault behavior, are also discussed.

DOI

10.1109/ATS64447.2024.10915272

Publication Date

1-1-2024

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