Performance Attacks on Branch Predictors in embedded processors with SMT support

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Conference Article

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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)


Designing efficient branch predictors has always been one of the top priority research tasks in computer architecture. In an embedded processor with support for multi-threaded execution, with multiple different applications executing in different threads, and managed by a single predictor, significant inter-application interference due to sharing of predictor data structures has been acknowledged to be a serious concern. In this paper, we show an attack methodology which exploits these shared structures for performance attacks on a benign application. In particular, we propose a methodology for creating a variant of a benign application, which when dispatched in a concurrently executing thread, can definitively slow down the performance of the benign one. We report the effect of such attacks with experiments on the Siemens software benchmarks.

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