A topology-agnostic test model for link shorts in on-chip networks

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Conference Article

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2016 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2016 - Conference Proceedings


With the ever-shrinking global geometries on a die and the concomitant rise in the complexity of interconnections in an on-chip network (NoC), the links used therein often suffer from various manufacturing defects such as shorts. These defects not only cause logical or functional errors but also give rise to various other system level failures such as duplication, misrouting, or dropping of a packet, thereby impacting the performance of the network significantly. This paper proposes an on-line test method that detects the presence of pairwise-shorts, if any, and identifies the faulty links. Several performance metrics are evaluated to demonstrate the impact of these faults, and simulation results demonstrate 100% coverage. The proposed method scales well to large-size NoCs irrespective of the topology and link-width.

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