Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs

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Conference Article

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Proceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017


The advent of 3D IC technology facilitates fabrication of large logic circuits on low area yet high performance chips. For a 3D IC, placement followed by assignment of Through-Silicon-Vias (TSV)s is a challenging problem involving various issues like inter-layer wirelength, power density, congestion and variation in surrounding carrier mobility. Each of the existing techniques for placement of TSVs deals only with a subset of these issues. In this paper, we propose an evolutionary approach MO-TSV to handle this multi-objective optimization problem. Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS'85 and ISCAS'89 benchmarks yield solution quality aswell as convergence times, which are encouraging.

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