Design of a parallel adder circuit for a heavy computing environment and the performance analysis of multiplication algorithm

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Conference Article

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Proceedings - 7th IEEE International Advanced Computing Conference, IACC 2017


Firstly, this study proposed a new parallel adder circuit model in Carry Value Transformation (CVT)-Exclusive OR (XOR) paradigm. Secondly, an efficient multiplication algorithm is discussed along with its performance analysis on various inputs selection. Our design of proposed model for the addition of many integer pairs using parallel Cellular Automata Machines (CAMs) can perform the addition in a much better way with setting a preprocessing testing logic in it. CVT and XOR operations together can do the efficient addition of two non-negative integers for any bulk inputs using CAM. Multiplication is the repetitive addition process, which could be designed using recursive use of CAM. Our analysis up to 10 bits selection of all integer pairs suggest that the recursive use of CAM for multiplication becomes much faster in real life scenario for any types of inputs. Further exponential operation is highly needed for various fields of computer science which is also described in this paradigm.

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