Date of Submission

10-28-2002

Date of Award

10-28-2003

Institute Name (Publisher)

Indian Statistical Institute

Document Type

Doctoral Thesis

Degree Name

Doctor of Philosophy

Subject Name

Computer Science

Department

Applied Statistics Unit (ASU-Kolkata)

Supervisor

Roy, Bimal Kumar (ASU-Kolkata; ISI)

Abstract (Summary of the Work)

In this dissertation, we consider the following combinatorial problems: some character- ization, enumeration, construction and optimization problems in both VLSI linear and VLSI two-dimensional arrays; and construction of two combinatorial designs as used by statisticians: nearly strongly balanced uniform repeated measurements designs (NSBUR- MDs) and balanced near uniform repeated measurements designs (BNURMDS). We give below, chapter-wise, the problems considered and a brief outline of the solutions.1.1 Enumerating Catastrophic Fault Patterns in VLSI Linear Arrays with Bidirectional or Unidirectional LinksSystolic systems consist, of a large mimber of identical and elementary processing element locally conuccted in a regular fashion. Each element receives data from its neighbor. computes and then sends the results again to its neighbors. Few particular elements1.1 ENUMERATING CATASTROPHIC FAULT PATTERNSLocated at the extremes of the systems (these extremes depend on the particular system) are allowed to communicate with the external world.The simplest systolic model is the VLSI linear array. In such a system the processing ekments (PRa) are connocted in a linear fashion: procesing elements are arranged in Enear order and each element is connected with the previous and the following element. Figure 1.1 shows a linear array of processing elements.PE PE PE (PE (PE) PE (PE) PE (P) to Figure L.1: VISI linoar array.Despite their simplicity, VLSI linear arrays have been uved to solve several problems. It is well-knowa how to use a VLSI liarar array for the matrix-vector muitiplication; several other numerical problems ( eg convulutions, triangular lincar systems) have been solved usiag VLSI linear arays (see, for example j8tj). The se of VLSI linear arrays is not, limited to mumetical problems. For example, various algorithms that solve the kongest eommon sabsequence prublem on a VLSI array have heen devised [57]Fanlt tolersnt techniques are very important to systolie systems. Here we sssume that only processors can fail. Indeed, since the number of processing elements is very large, the probability that a set of procrssing elements becomes faulty is not amall. In a linear srray of N procesing elements, one faulty element is sufficient to stop the flow of information from ane side ta the other. Without the provision of fault-tolerance enpgbilities, the yiekl of VLSI chips for soch an arthiterture would be so poor that the chip would be unacceptable. Thus, faalt-tolerant mechanisms must be provided in order to avold faolty processitg elements taking part in the computation. A widely used technique to achieve recontigurability consists of peoviding redundancy to the desired architecture (8, 14, 52).1.1 ENUMERATING CATASTROPHIC FAULT PATTERNSIn VLSI linear arrays the redundancy consists of additional processing elements, called spares, and additional connections, called bypass links. Bypass links are links that connect each processor with another processor at a fixed distance greater than 1. The redundant processing elements are used to replace any faulty processing element; the redundant links are used to bypass the faulty processing elements and reach others.

Comments

ProQuest Collection ID: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:28843032

Control Number

ISILib-TH125

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

DOI

http://dspace.isical.ac.in:8080/jspui/handle/10263/2146

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